The present invention relates to a planar redistribution device or structure for directly attaching an integrated circuit chip or chips to a printed circuit board or card. In addition, the present invention also relates to a process for fabricating such a planar redistribution device.
With the advent of relatively large, high performance integrated circuit systems, continuing efforts are underway to optimize packaging topology. One way of accomplishing this is to form a printed circuit board or card by laminating together one or more signal layers and one or more power planes or cores and then directly attaching one or more semiconductor chips to the laminate so formed thereby forming a completed chip carrier. Because the electrical contacts or bumps on a typical semiconductor chip are so close together, it is usually necessary to interpose some form of redistribution structure between the chip and the printed circuit board or card for expanding the areas over which electrical contacts between the chips and the printed circuit board or card are made. For example, see U.S. Pat. No. 5,418,689, to Alpaugh et al., the disclosure of which is incorporated herein by reference.
In manufacturing devices such as illustrated in the above noted Alpaugh et al. patent, the individual signal layers and power planes are first produced and tested. Those meeting specifications are then laminated together to form a substrate. Thereafter, a redistribution device is built up thereon by means of a step-by-step operation using conventional printed circuit board manufacturing techniques. After optional testing again to see if specifications are met, the semiconductor chip or chips are mounted thereon.
With the ever increasing demands for improved reliability and better performance at lower cost, there still exists a need for improved designs and manufacturing techniques for producing direct mounted printed wiring devices.